Making SIMD Code Scale to Any Vector Width

Stream HPC shows how to make SIMD code scale with vector width by storing vector components as lanes, one object per lane, instead of one vec3/vec4 per object. In a frustum-culling example on a Ryzen 7 5800 with Clang, cost fell from 13.4 ns to 0.67 ns per box on AVX2 and 1.84 ns on SSE. Gains came from splatting planes once outside the loop and writing results a block at a time.