Core to core is not core to core
Comments on “Core to core is not core to core”
Claim-checked. Scored by all three judges, and its checkable claims were compared with the sources it cites. How far stories are checked
Jacen Li reports that core-to-core latency on mesh-based Intel and Arm server chips depends on the physical address as well as the two cores, because each line's coherence "home" slice relays the transfer. Across the machines tested, best-to-worst lines differ by about 14 to 30 ns. Pinning rigtorp's SPSC queue lines to fast addresses cut round trips about 12 to 38% and shrank run-to-run variance. These figures are the author's own, from one benchmark and a limited set of machines, and not independently verified.
Why it ranked
No. 12 of 137 with a score of 0.68. The panel rated it highest on technical depth (0.97) and substantiated (0.93), lowest on audience breadth (0.48). Placed No. 12, No. 18 by score alone: the placement terms moved other stories past it.
- AI judgeJudge 2claude-haiku-5-5
- Deep, well-measured hardware microarchitecture study on cache-coherence homing latency with reproducible methods and practical allocator gains; niche audience but substantive and new to recent coverage.
- AI judgeJudge 3gpt-5.6-luna
- A deeply technical, measured investigation shows physical-address-dependent cache-coherence homing, benchmark methodology, cross-CPU results, and substantial queue improvements. It is highly useful to systems programmers, though primarily relevant to performance specialists rather than most builders.
Each judge wrote its line after answering the rubric, with the site and the author still hidden. Every answer behind this is in the table under Score.
Score
0.68total under rubric v2.3
- Significance0.57
- Reader interest0.79
- Audience breadth0.48
- Practical relevance0.70
- Substantiated0.93
- Technical depth0.97
- New information0.91
- Counts against: Promotional0.03
- Counts against: Overclaim0.14
Each judge’s answer per question (0–1), their mean and spread, and what the question adds to the score (weight × mean).
| Question | Judge 1 | Judge 2 | Judge 3 | Mean | Spread | Weight | Contribution (weight times mean) |
|---|---|---|---|---|---|---|---|
| SignificanceHow much does this change what people in tech know or can do? | 0.52 | 0.40 | 0.78 | 0.57 | 0.38 | +0.24 | +0.136 |
| Reader interestWould a well-informed senior engineer or tech founder want to read this today, and likely pass it on? | 0.63 | 0.82 | 0.93 | 0.79 | 0.30 | +0.26 | +0.206 |
| Audience breadthHow many people who build technology does it concern? | 0.48 | 0.45 | 0.50 | 0.48 | 0.05 | +0.13 | +0.062 |
| Practical relevanceHow useful is it to someone who builds software or tech products? | 0.69 | 0.60 | 0.82 | 0.70 | 0.22 | +0.22 | +0.155 |
| SubstantiatedHow well is it backed? Consider whether it is the primary source, and whether its main claims come with data, code, a demo, a reproducible method or citations. | 0.98 | 0.88 | 0.94 | 0.93 | 0.10 | +0.05 | +0.047 |
| Technical depthHow technically substantive is it? | 1.00 | 0.94 | 0.98 | 0.97 | 0.06 | +0.05 | +0.049 |
| New informationDoes it contain information absent from the stories covered in the last 7 days (list provided)? | 0.89 | 0.85 | 0.99 | 0.91 | 0.14 | +0.05 | +0.046 |
| PromotionalIs it mainly marketing with little substance (a press release, ad or sponsored post with no real information)? A launch post that carries real news is not promotional. | 0.04 | 0.03 | 0.01 | 0.03 | 0.03 | −0.19 | −0.005 |
| OverclaimDo the headline or conclusions claim more than the body supports? | 0.24 | 0.12 | 0.06 | 0.14 | 0.18 | −0.11 | −0.015 |
| Sum of contributions | +0.679 | ||||||
| Claim-check penalty | 0.000 | ||||||
| Total, as published | 0.679 | ||||||
Spread is the highest minus the lowest judge answer. marks a spread above 0.40: the judges disagree, and the story is marked contested.
The badge for this ranking, for the author's page or anyone's: one line of HTML, and it links back here.
<a href="https://rubric.hrih.si/editions/2026-11-04/12/"><img src="https://rubric.hrih.si/badge/2026-11-04/12.svg" alt="Ranked #12 on Rubric, 4 Nov 2026" width="238" height="28"></a>Claim check
Claim check: 7 no source given · 1 couldn’t check. Each claim is compared with the source the article itself cites; a flag is published only when both checkers agree.
Couldn’t checkNumber
On the Xeon 6314U, the home hash is an XOR of physical address bits 6 to 36, per McCalpin's research on mapping addresses to L3/CHA slices in Intel processors.
The source was unreachable, paywalled or too long, or the two checkers disagreed.
The article says “On the Xeon 6314U, the home hash is an XOR of PA bits 6 to 36, using McCalpin's research”
The source says No passage could be compared.
Source cited by the article: repositories.lib.utexas.edu/bitstream/handle/2152/87595/TR-2021-03_IntelAddressHashing.pdf
No source givenCausal conclusion
The author found no evidence of direct cache transfer on this CPU using mesh counters; all data was forwarded through the home.
The article gives no link or citation for it.
The article says “Using mesh counters, I did not see any evidence of direct cache transfer, and instead, all data was forwarded through the home”
The source says No source to compare with.
No source givenNumber
With a fixed home, the standard deviation of core to core latency tests drops to 0.1 ns from about 5 ns, so most run to run variation comes from homing.
The article gives no link or citation for it.
The article says “while the standard deviation of these core to core latency tests is ~5 ns, with a fixed home, the std drops to 0.1 ns”
The source says No source to compare with.
No source givenNumber
The CAS benchmark has a slope of 0.91 ns per hop, while the pointer chase has a slope of 1.57 ns.
The article gives no link or citation for it.
The article says “The CAS benchmark has a slope of 0.91 ns per hop, while the pointer chase has a slope of 1.57 ns”
The source says No source to compare with.
No source givenNumber
Best-to-worst line core to core latencies measured for a typical pair: Sapphire Rapids 49 to 72 ns, Granite Rapids 89 to 118 ns, Graviton4 39 to 53 ns, Graviton5 53 to 83 ns.
The article gives no link or citation for it.
The article says “Sapphire Rapids (four chiplets) 49 to 72 ns. Granite Rapids (6975P-C, three dies) 89 to 118 ns. Graviton4 (Arm CMN) 39 to 53 ns. Graviton5 53 to 83 ns”
The source says No source to compare with.
No source givenNumber
Placing the hot lines of rigtorp::SPSCQueue on fast addresses with a custom allocator cut round trip latency by about 12 to 38%.
The article gives no link or citation for it.
The article says “This cut round trip latency by ~12 to 38%”
The source says No source to compare with.
No source givenBenchmark result
Fast address placement won 149 of 160 rounds on Ice Lake and 155 to 160 of 160 on the other machines.
The article gives no link or citation for it.
The article says “fast address placement won 149 of 160 rounds on Ice Lake and 155 to 160 of 160 on the others”
The source says No source to compare with.
No source givenNumber
Within an AMD Zen chiplet, lines are flat and placement gains 0–4%, while across chiplets latency is about 6× and varies per line.
The article gives no link or citation for it.
The article says “within a chiplet the lines are flat and placement gains 0–4%; across chiplets latency is about 6× and does vary per line”
The source says No source to compare with.
Also covered by
No other coverage was clustered with this story.
Elsewhere
Elsewhere: HN 3 pts, not on front page
Recorded for context only, checked 4 Nov 2026, 05:47 UTC. It played no part in the ranking.