Core to core is not core to core

Jacen Li reports that core-to-core latency on mesh-based Intel and Arm server chips depends on the physical address as well as the two cores, because each line's coherence "home" slice relays the transfer. Across the machines tested, best-to-worst lines differ by about 14 to 30 ns. Pinning rigtorp's SPSC queue lines to fast addresses cut round trips about 12 to 38% and shrank run-to-run variance. These figures are the author's own, from one benchmark and a limited set of machines, and not independently verified.